TY  - JOUR

T1  - High Speed and Low Latency ECC Implementation over GF(2m) on FPGA

JO  - IEEE Transactions on Very Large Scale Integration Systems

UR  - http://eprints.whiterose.ac.uk/99476/

PY  - 2016/06/14

AU  - Khan ZUA

AU  - Benaissa M

ED  - 

DO  - DOI: 10.1109/TVLSI.2016.2574620

VL  - 25

IS  - 1

SP  - 165

EP  - 176

Y2  - 2024/12/20

ER  -