TY  - JOUR

T1  - Design of a Snubber Circuit for Low Voltage DC Solid-State Circuit Breakers

JO  - IET Power Electronics

PY  - -0001/11/30

AU  - Madathil S

AU  - Wang Z

ED  - 

PB  - Institution of Engineering and Technology

Y2  - 2024/12/20

ER  -