@article{article, title  = {{Power-delay-area efficient modulo 2(n)+1 adder architecture for RNS}},

 url = {{}},

 year = {{2005}},

 month = {{3}},

 author = {{Patel RA and Benaissa M and Boussakta S and Powell N}},

 doi = {{10.1049/el:20056837}},

 volume = {{41}},

 journal = {{ELECTRON LETT}},

 issue = {{5}},

 pages = {{231-232}},

 note = {{Accessed on 2024/12/20}}}