TY  - JOUR

T1  - Fast parallel-prefix architectures for modulo 2(n)-1 addition with a single representation of zero

JO  - IEEE T COMPUT

PY  - 2007/11/01

AU  - Patel RA

AU  - Benaissa M

AU  - Boussakta S

ED  - 

DO  - DOI: 10.1109/TC.2007.70750

VL  - 56

IS  - 11

SP  - 1484

EP  - 1492

Y2  - 2024/12/20

ER  -