TY  - CONF

T1  - High-speed pipelined ECC processor on FPGA

JO  - 2006 IEEE WORKSHOP ON SIGNAL PROCESSING SYSTEMS DESIGN AND IMPLEMENTATION

PY  - 2006/01/01

AU  - Chelton W

AU  - Benaissa M

ED  - 

SP  - 136

EP  - 141

Y2  - 2024/12/20

ER  -